I’m a postdoc at UC Berkeley in EECS in Christopher W. Fletcher’s group. Before, I was a PhD student at ETH Zurich for 3 fun years, got an ITET Master’s degree from ETH Zurich and an Ingénieur Polytechnicien degree from École Polytechnique.
email: first dot last at berkeley.edu
Research
I am interested in many aspects of hardware security such as information flow tracking, fuzzing, rowhammer and formal verification.
Flagship projects
My flagship projects at COMSEC (ETH) are:
- Lost in Translation (USENIX Security ‘25 - open source): fuzzing to find hardware translation (MiRTL) bugs in EDA software and exploiting them.
- Cascade (USENIX Security ‘24 - artifacts evaluated): a black-box CPU fuzzer that outperforms all previous coverage-guided fuzzers.
- CellIFT (USENIX Security ‘22 - artifacts evaluated): scalabe information flow tracking for hardware.
- RemembERR (MICRO ‘22 - artifacts evaluated): a comprehensive survey of x86 errata.
Tapeouts
At IIS at ETH (under Luca Benini) I co-conducted the tapeout of:
Information flow tracking
At COMSEC (ETH):
- μCFI (CCS ‘24 - artifacts evaluated): CellIFT+formal->first reported IFT-based hardware CVE discovery.
- HybriDIFT (ICCAD ‘24 - open source): approximate high-level implicit flows.
Memory security
At COMSEC, I was also involved in memory security research:
- HIFI-DRAM (ISCA ‘24 - open source): DRAM imaging for sense amplifier analysis (best paper nominee).
- ZenHammer (USENIX Security ‘24 - open source): Rowhammer on AMD Zen CPUs - first reported DDR5 bit flips.
- REGA (IEEE Symposium on Security and Privacy ‘23 - open source): a Rohwammer defense based on a new sense amplifier design.
- ProTRR (IEEE Symposium on Security and Privacy ‘22 - open source): a Rohwammer defense based on on-chip counters.
Body Area Networks
At STMicroelectronics (under Andreia Cathelin) and BWRC (under Jan Rabaey), I worked on body area networks:
- HB-MAC (IEEE Access ‘20): a MAC protocol for heartbeat-based HWBANs.
- Heartbeat-Based Synchronization (ISCAS ‘20): use human heartbeat as HWBAN sync signal.
Supervision
At ETH Zurich, I’ve supervised the following students:
- Matej (Master’s thesis ‘24)
- Tobias (Master’s thesis ‘24)
- Quentin (Semester thesis ‘24)
- Tobias (Semester thesis ‘23)
- Sandro (Master’s thesis ‘23)
- Tristan (Master’s thesis ‘23)
- Adriel (Master’s thesis ‘23)
- Valentin (Semester thesis ‘22)
- Quentin (Bachelor’s thesis ‘22)
- Adriel (Semester thesis ‘22)
- Guillaume (Semester thesis ‘22)
- Maximilian (Master’s thesis ‘22)
- Stijn (Master’s thesis ‘22)
- Floris (Semester thesis ‘21)
Community service
Reviews:
- Top Picks in HES’24.
- CCS’25.
Sub-reviews:
- CCS’21.
- USENIX ATC’22.
- DIMVA’23.
- HPCA’25.
Teaching
I’ve been a teaching assistant for the following courses at ETH Zurich:
- Computer Engineering ‘22, ‘23, ‘24 (ETH Zurich)
- VLSI 1: HDL Based Design for FPGAs ‘20 (ETH Zurich)
Other projects
- Simulated memory controller (GSoC ‘20).
- Some Android games (FlaviBird, GraviTree).