Enter, Exit

Testing Isolation Boundaries for Microarchitectural Leaks.

TL;DR

Our paper introduces an end-to-end platform for stress-testing microarchitectural isolation between security domains. By extending model-based relational testing to multiple “actors” (processes, VMs, kernels), the tool:

Why “Enter, Exit”?

Isolation boundaries are crossed constantly: VMENTER, SYSCALL, page-fault handlers, etc. But microcode and speculative helpers execute behind the scenes. Enter, Exit turns those normally opaque transitions into a fuzzing surface:

“We solve these challenges by introducing an actor framework … one actor can transition to another by executing a specific instruction sequence (e.g., syscall or VM-enter).”

Key Idea

  1. Actors = security domains (host, VM, user, …).
  2. Templates define transition choreography; the generator splices in random instructions around the mandatory sequences.
  3. Executor (a lightweight kernel module) instantiates VMs, page tables, fault-handlers, & trace-collection at hundreds of tests per second.
  4. Contracts specify what a victim may leak; any extra information in the hardware trace is flagged.

The Actor Framework in One Picture

Host (kernel) ─┐
│ VMEXIT
Guest VM 1 ────┤
│ VMENTER
Guest VM 2 ────┘ ← observer

Templates let us swap Host/User, add mitigations (e.g., VERW), or alias memory with a single YAML knob, then blast 100 k randomised programs per template.

What We Found

Leak class Short description CVE / status
Cross-VM cached-line leak Victim’s cached byte modulates attacker timing via dual page-fault gadget CVE-2024-36357
Kernel-store echo Last ≈ 32 kernel stores observable from user mode CVE-2024-36350
Rogue read of RDTSCP.AUX RDTSCP speculates past CR4.TSD CVE-2024-36349
Speculative SMSW under UMIP AMD CPUs return lower 16 bits of CR0 CVE-2024-36348

(Full disclosure timeline and patches in AMD-SB-7029.)

Validating Defenses

Because templates are first-class, we could prepend mitigations and immediately retest:

Performance at a Glance

Paper & Code

FAQ

Q: Is this only for x86? A: No. The framework cleanly separates generation, execution and contract layers; porting the executor to ARM/RISC-V is mostly engineering work.

Q: Can I use this like a fuzzer for my mitigation patch? Yes, drop your patch into a macro, point the victim actor to it, and see if any leaks survive.

Q: What if I just want a PoC for my newly discovered gadget? Write the gadget as a template, mark the leak you expect allowed in the contract, and publish the minimal repo; others can reproduce in minutes.


Acknowledgements

We would like to thank Adrien Ghosn and Kaveh Razavi for the discussions and support they provided. We also thank our shepherd and the anonymous reviewers for their valuable feedback. We are grateful to AMD and Intel PSIRT teams as well as Microsoft Security Response Center for their prompt responses and the constructive discussions we had while reporting the vulnerabilities. This research was supported by the Swiss State Secretariat for Education, Research and Innovation under contract MB22.00057 (ERC-StG PROMISE).